In conventional double data rate (DDR) memories, data and data strobe signals (i.e., DQS) are returned from a memory module during each read cycle. The data strobe signal DQS is a bidirectional signal. Noise or unwanted signal toggling may propagate into a memory controller when the controller is not actively reading data from the memory module. Referring to FIG. 1, an example of a circuit 10 illustrating a conventional data strobe architecture for double data rate (DDR) memory is shown. Conventional approaches lack a programmable coarse delay in a first data rate domain.
It would be desirable to implement a data strobe enable architecture suitable for use in a double data rate (DDR) memory application that provides a programmable coarse delay in a first data rate domain.